SAN JOSE, Calif. -- Altera Corporation (NASDAQ:ALTR) today announced the immediate availability of the Nios™ II integrated development environment (IDE), based on the open and extensible Eclipse platform. This platform has become the preferred development framework among leading embedded tool providers such as Wind River and QNX and was selected by EDN magazine as one of the top 100 new products of 2003."The Nios II processor provides substantially better resource utilization than its predecessor, which enables us to add functionality to the existing Cyclone FPGA in our RECAPS (Remote Energy Consumption Acquisition Processor System) wireless reading solution without incurring hardware respin costs," said Martin Forsberg Lie, software architect at Wireless Reading Systems. "Further, the Nios II integrated development environment (IDE) delivers every element we could hope for, and will reduce our software engineering time. By enabling us to add features and support RECAPs with greater efficiency, the Nios II processor provides us with the means to deliver greater value to our customers while keeping our costs to a minimum."
Robust Software Tool Suite
The Nios II IDE provides a complete C/C++ software development suite including a text editor, project manager and build tools, debugger, and CFI (Common Flash Interface) compatible flash programmer. The debugger connects to a wide range of targets, including the FPGA hardware (via JTAG cable), the Nios II Instruction Set Simulator, and the ModelSim®-Altera software to provide the ultimate in flexible debug scenarios. Support for power features of the Nios II on-chip instrumentation core are also provided including:
-- Two hardware execution breakpoints -- useful for debugging firmware code stored in ROM or Flash memory. -- Two data triggers with bit mask and range facilities -- ideal for tracking down code that accesses critical data. -- 128 frames of on-chip trace with source-level reconstruction.
Because it is based on Eclipse, software "plug-ins" are easily deployed to provide additional functionality. Included with the Nios II IDE are plug-ins that support the MicroC/OS-II real-time operating system (RTOS) by Micrium, and Lightweight IP open source TCP/IP stack. Nios II developers can easily incorporate these software tools from within the Nios II IDE environment, to build multi-tasking and/or network enabled applications.
"Processor selection for systems with performance similar to Nios II is influenced more by the software team than the hardware team," said Tim Allen, Altera's senior director for embedded processor development. "Developers today not only desire, but expect a modern IDE for embedded systems development, and that's what we are delivering."
Enhanced Debug Features Available from First Silicon Solutions
First Silicon Solutions (FS2) adds support for Altera's Nios II family of processors with two product offerings. The Nios II Debug Upgrade, available for download from the web, adds to the Nios II IDE two more hardware execution breakpoints, two more data triggers, and increases on-chip trace buffer from 16 to 128 frames. The FS2 JTAG-based trace probe, ISA-Nios/T, provides 128K frames of off-chip processor trace, connecting to the developer's host PC via parallel or USB port for debugging more complex software applications. For more information, visit http://www.fs2.com/isa-nios.html .
Pricing and Availability
Nios II IDE will be available with each Nios II development kit (Stratix, Stratix Pro and Cyclone editions). All active Nios subscribers will automatically receive Nios II IDE as part of their Nios II update. Nios developers with inactive subscriptions can receive this and 12 months of updates for only $495.
About the Nios II Family of Embedded Processors
Altera's Nios II family of soft-core embedded processors is optimized for programmable logic and system-on-a-programmable-chip (SOPC) integration. With three Nios II cores and multiple FPGA device families to choose from, developers can accommodate a wide range of performance and price points. The Nios II cores are general-purpose RISC processors that can be combined with user logic and programmed into an Altera FPGA. The processor features a 32-bit instruction set, 32-bit data path, and configurable instruction and data caches. Nios II embedded processors are royalty free when used in Altera PLDs and HardCopy™ devices. An ASIC license for OEM applications is available for an additional charge. For more information, visit www.altera.com/nios.
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