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Creating QNX BSP for Xilinx Ultrascale Eval board

QNX Application portings.

Creating QNX BSP for Xilinx Ultrascale Eval board

Postby AshiGupta » Wed Dec 19, 2018 8:00 am

Hi,

I am running QNX 7.0 BSP over Xilinx Ultrascal evaluation board. QNX BSP for this specific board is available on QNX website, however there are some drivers which are not yet incorporated in BSP.
I want to access AXI bus of Xilinx using QNX Application i.e. read and with on AXI memory using AXI APIs which are available in xil_io.h which gets generated when we create hardware platform for this board in Vivado.
What i want to learn here is how i can update or link QNX BSP with with these AXI APIs / AXI driver to perform AXI transaction using QNX Application?
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Re: Creating QNX BSP for Xilinx Ultrascale Eval board

Postby nico04 » Wed Dec 19, 2018 8:30 am

Generally speaking, you don't need a driver to access hardware in a QNX process.
Can you post the content of xil_io.h (don't forget to use Code tags) ?
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Re: Creating QNX BSP for Xilinx Ultrascale Eval board

Postby AshiGupta » Wed Dec 19, 2018 11:55 am

Hi, Below are the few functions written in xil_io.h

static INLINE u32 Xil_In32(UINTPTR Addr)
{
return *(volatile u32 *) Addr;
}

static INLINE u64 Xil_In64(UINTPTR Addr)
{
return *(volatile u64 *) Addr;
}

static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
{
volatile u16 *LocalAddr = (volatile u16 *)Addr;
*LocalAddr = Value;
}

static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
{
volatile u32 *LocalAddr = (volatile u32 *)Addr;
*LocalAddr = Value;
}

But this file is included in BSP which is generated from Xilinx hardware platform and is not available in QNX7.0 BSP.
Also i am not sure about this but i believe even if we use mmap to read / write on memory location, we need AXI driver in BSP.
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Re: Creating QNX BSP for Xilinx Ultrascale Eval board

Postby nico04 » Wed Dec 19, 2018 12:49 pm

this file is included in BSP which is generated from Xilinx hardware platform

What does this BSP refer to ? A linux BSP generated from Xilinx tools ?

Code: Select all
 and is not available in QNX7.0 BSP

Unless your QNX BSP needs it, there is no reason to embed this file in it.

You can use it directly in your apps.
Regarding its simplicity, you might not need it at all.

Just mmap the AXI bus memory region in your code and read/write directly.
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Re: Creating QNX BSP for Xilinx Ultrascale Eval board

Postby AshiGupta » Wed Dec 19, 2018 2:59 pm

i have tried using mmap_device_memory and got virtual address for the physical address i have passed but as soon as i try reading or writing anything on that address, CPU hangs and i need to reset the system.

This is how i am using mmap_device_memory API and reading value from address

pVirtualAddress = (int*)mmap_device_memory(nullptr,
0x4,
PROT_READ | PROT_WRITE | PROT_NOCACHE,
0,
0xD0000004);

if(pVirtualAddress != MAP_FAILED)
{
test = *pVirtualAddress; // CPU hangs here
cout <<"Virtual Address : " << pVirtualAddress << "\n";
cout << "Virtual address data: "<< test << "\n";
}
else
{
perror( "mmap_device_memory for physical address failed" );
exit( EXIT_FAILURE );
}
Last edited by AshiGupta on Wed Dec 19, 2018 3:03 pm, edited 1 time in total.
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Re: Creating QNX BSP for Xilinx Ultrascale Eval board

Postby AshiGupta » Wed Dec 19, 2018 3:03 pm

nico04 wrote:
this file is included in BSP which is generated from Xilinx hardware platform

What does this BSP refer to ? A linux BSP generated from Xilinx tools ?

Code: Select all
 and is not available in QNX7.0 BSP

Unless your QNX BSP needs it, there is no reason to embed this file in it.

You can use it directly in your apps.
Regarding its simplicity, you might not need it at all.

Just mmap the AXI bus memory region in your code and read/write directly.


This BSP is created using Xilinx hardware platform which gets generated from the block design in Vivado.
AshiGupta
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Posts: 24
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Re: Creating QNX BSP for Xilinx Ultrascale Eval board

Postby nico04 » Wed Dec 19, 2018 3:40 pm

I have no knowledge of Zynq system but I guess AXI bus has to be initialised.
Have you checked this initialisation is done somewhere ?
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Re: Creating QNX BSP for Xilinx Ultrascale Eval board

Postby AshiGupta » Thu Dec 20, 2018 9:29 am

nico04 wrote:I have no knowledge of Zynq system but I guess AXI bus has to be initialised.
Have you checked this initialisation is done somewhere ?


There is no AXI initialization done in QNX BSP. I am not sure if i need to initialize AXI bus in my firmware code
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Re: Creating QNX BSP for Xilinx Ultrascale Eval board

Postby nico04 » Thu Dec 20, 2018 10:11 am

I believe the AXI bus has to be configured before accessing it.
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